EEPROM cells make use of a dual gate structure to place an electric field over a field region between two p+ composite regions. The p+ composite regions are commonly referred to as drain and source regions since the structure is essentially a dual gate PMOS transistor.
EEPROMs typically come in one of two configurations: stacked EEPROM, as shown in FIG. 1, and free EEPROMs as shown in FIG. 2. The stacked EEPROM structure of FIG. 1 includes two polygates 100,102 stacked on top of each other. The top gate 100 is connected to a voltage source while the lower gate 102 is not externally connected and is thus floating. The gates 100, 102 are separated by an oxide 104, thus when a voltage is applied to the gate 100, the two gates act as a first capacitor. Similarly, the lower gate 102 is spaced from the active region 106 by a gate oxide, or tunneling oxide 108, thereby creating a second capacitor, which is formed in series with the first capacitor. Typically, the areas of the oxide regions 104, 108 are chosen so that the capacitance of the first capacitor (formed by the two gates 100, 102) is substantially larger (typically >5 times larger) than the capacitance of the lower (second) capacitor (formed by the lower gate 102 and the active region 106). It will be appreciated that oxide thickness can also be chosen to adjust the capacitance ratio. Thus when a voltage is applied to the top gate 100, a lower voltage (10× lower in the case where the top capacitor has 10× the capacitance of the lower capacitor) will appear across the lower capacitor. As part of the active region 106 are p+ composite regions on either side of a well. These composite regions define a drain region 110, and a source region 112 of a transistor.
FIG. 2 shows a plan view of a free EEPROM 200. In this configuration the first capacitor 202 is formed laterally spaced from the second capacitor 204. The first capacitor 202 is again substantially larger than the second capacitor 204, as is discussed in more detail below. In this case, however, they share one continuous common polysilicon floating gate region 206. The second capacitor 204 is defined by the common floating gate 206 separated by an oxide layer 320, from an active region (in particular from an n-well 300), as shown in FIG. 3. FIG. 3 is a sectional view of the left hand portion of the EEPROM 200 along the line A—A. As can be seen from FIG. 3, this left hand portion defines a PMOS transistor with p+ drain and source regions 302, 304 on either side of the n-well 300. FIG. 4, in turn, shows a section along B—B of the right hand portion of the EEPROM 200. The right hand portion also defines a PMOS transistor. In this case the p+ regions 210 formed on either side of an n-well 410, form a second active region to define a control gate (non-floating gate). The control gate 210 is provided with a control gate contact 420. As mentioned above, the first capacitor 202 is substantially larger than the second capacitor 204. This is achieved, in this free EEPROM configuration, by means of the E-shaped polysilicon region 206, which provides a large periphery and thus a large capacitor area, best seen in the plan view of FIG. 2. The capacitor 202 is thus defined by the control gate 210 separated by the oxide region 320 from the floating gate 206. The location of the contact 420 of the control gate 210 is indicated in FIGS. 2 and 4. The control gate 210 serves to erase the EEPROM, as is discussed in greater detail below, and the floating gate 206 is used for programming the EEPROM.
In order to better appreciate the purpose of the capacitors in an EEPROM cell, it is useful to consider the three modes that an EEPROM can operate in: program mode, erase mode, read mode.
The read mode seeks to determine the state of a memory cell by supplying the first polygate with a certain read voltage and monitoring the drain current. In the case of the stacked configuration the drain current is the current flowing between drain 108 and source 110, and in the case of the free configuration, it is the current flowing between drain 302 and source 304. In order to affect the drain current so as to distinguish between a programmed memory cell and an unprogrammed cell, the cells in an array structure are first erased and then selectively programmed.
Program Mode:
During the program mode, in order to program a memory cell, a programming voltage, e.g. 10V is applied to the non-floating gate (gate 100 in the case of the FIG. 1 configuration, and gate 200 in the case of the FIGS. 2–4 configuration). Due to the capacitor ratio, which is 10:1 in the example discussed above, 10V applied to the gate 100 or gate 200 appears as approximately 1 V across the second capacitor. The resultant electric field across the second capacitor attracts electrons. Thus, it provides hot electron injection into the second (floating) gate. Thus, once programmed, there is an electron charge on the floating gate 102, 202.Read mode: In order to read a cell, a relatively small read voltage, e.g. 1V, is applied to the control gate 100, 210. This voltage provides a voltage of about 0.1V across the second capacitor and has the effect of attracting any electrons that were injected into the floating gate. By attracting the electrons in the floating gate sufficiently strongly, the electric field across the second capacitor is reduced, allowing drain current to flow. It will be appreciated that in the case of an unprogrammed cell, where there is essentially no charge on the second capacitor, very low gate voltage will suffice to produce drain current. Also, in the case of a programmed cell, it will be appreciated that depending on the amount of charge on the second capacitor the read voltage required to achieve drain current flow will vary. For any particular cell, a read voltage can thus be chosen at which drain current will flow for an unprogrammed cell but where the voltage is not large enough to achieve drain current in the case of a programmed cell, i.e., the read voltage lies between the threshold voltage Vth for a programmed cell and the Vth for an unprogrammed or erased cell.
However, due to minor structural variations between memory cells in an array, the threshold voltages will vary. For example, varying amounts of nitride impurities in the oxide 108, 320 will result in varying numbers of electron and/or hole traps in the oxide, thereby affecting the threshold voltages. Thus different cells in an array will have different electric fields across their floating capacitors and will require different threshold voltages Vth to achieve drain current flow. This is best illustrated by the Vth curves across an array (in this case a die defining an array of memory cells), as shown in FIG. 5. The upper curve 500 shows the varying threshold voltages to achieve drain current flow when the cells are programmed. The lower curve 502 shows the varying threshold voltages to achieve drain current flow when the cells are not programmed. If a single threshold voltage is selected for reading all of the cells, e.g., the read voltage indicated by the broken line 504, it will be noted that some cells will provide a wrong result. For instance the cell defined by the threshold voltage 510 would not produce a drain current even if erased since its threshold voltage is higher than the chosen read voltage 504. Similarly, the cell next to it would provide incorrect results since it would always show a drain current at the chosen read voltage of 504, even if it is programmed (since not only is its threshold voltage when unprogrammed, but also its threshold voltage when programmed, lower than the chosen read voltage 504).
Erase Mode:
As mentioned above, prior to programming EEPROM memory cells, the entire array or, in some types of EEPROMs, entire sectors in the array are first erased. This is done by “sucking” off electrons from the floating gate by Fowler-Nordheim effect, which involves applying a large electric field to the top or bottom of the capacitor and pulling off the electrons. When sucking electrons off the top of the capacitor, this can be done by keeping the drain at 0V to avoid further electrons being injected in from the bottom of the floating gate, and applying a large positive voltage to the non-floating gate to suck off the electrons off the top through the non-floating gate by Fowler-Nordheim effect. Instead, the electrons can be sucked off the bottom by holding the non-floating gate at 0V and applying a large positive voltage to the drain 110, 302.
As discussed above, the variations between the cells in an array creates a problem when trying to use a single threshold voltage, as a threshold judgment criteria, to determine whether or not a cell is programmed or erased, i.e., using a single threshold voltage during the read operation, for all cells in the array.